Capacitors and thin film resistors are often incorporated in process technologies used for analog and mixed signal applications. Generally, in fabricating integrated circuits that include these components, the large-capacitance MIM capacitors are formed over the transistors at the metal level due to the area requirements of the capacitors.
A thin film resistor is a resistor formed from a relatively thin layer of resistive material. Numerous resistive materials, such as doped polysilicon, SiCCr and NiCr, have been used to form the resistive layer. Parameters important for a thin film resistor include the resistor value, tolerance of the resistor value, the temperature coefficient of resistance, and the ability of similarly formed resistors to have similar values, known as matching.
A conventional process sequence for forming both a MIM capacitor and a thin film resistor in a standard interconnect process flow requires three metal layers. Thus, if a conventional two layer metal process is used, either MIM capacitors or thin film resistors may be included but not both.
For example, for one currently implemented process, a metal stack is deposited on a semiconductor wafer substrate that has completed front-end processing through the first interconnect dielectric deposition and contact formation. Some examples of a typical metal stack are a stack of Ti (100 Å typical thickness), TiN (250 Å typical thickness), AlCu (10000 Å typical thickness), and TiN (500 Å typical thickness). The metal stack is then patterned and etched, followed by dielectric deposition and planarization.
A trench is then etched in the dielectric and filled with material that acts as a contact pad for the thin film resistor. One example of the trench fill material is AlCu (1500 Å typical thickness). Next, planarization of the trench fill is done. After planarization, material for the thin film resistor is deposited, patterned and etched. Some examples of thin film resistor material are SiCCr, NiCr, and TiW. Following this, dielectric is deposited and planarized. Contact to the thin film resistor is then provided through a thin film resistor via, which is formed by patterning, etching, and via filling.
A separate via formation to contact the metal stack is done next, with pattern, etch and via fill. A second metal deposition is done next to form a second metal stack. The second metal stack could be similar to the first metal stack in terms of layers used and their thicknesses. The second metal stack is used as a bottom plate for the MIM capacitor. MIM dielectric deposition is done next, followed by deposition of the MIM top plate, which may be AlCu with a thickness of about 1500 Å, for example. A window pattern and etch is then done to aid in alignment of the MIM pattern. Subsequently, the MIM pattern and etch are done to define the MIM capacitor. Connection to the MIM capacitor and thin film resistor are provided by doing the second metal stack deposition, pattern and etch. Thus, this conventional process for integrating a MIM capacitor and a thin film resistor uses a total of five masking steps.